JNTUH
SECOND BITS
STLD
Note: 1.Don’t think that these bits only
will be repeted in second mid.go through the concepts of last four units
thoroughly then solve bits .these bits to cross check your knowledge
1.The Programmable Array Logic
consists of [ d]
a) fixed OR and AND
gates b) Programmable OR , fixed AND gates
c) Programmable OR
and AND gates d) Programmable AND , fixed OR gates
2. A ring counter is useful in generating————- . [c ]
a) Frequency scaling b ) Pseud or and on
pattern generation
c) Timing signals d ) Refresh address of
DRAM
3. An ASM chart can be [ a]
a) converted to a
state diagram & table and implemented as a Flip-Flop
b) converted into a
state table
c) converted into
astate diagram
d) implemented
using gates & flip – flops
4. Four RAM chips of 16×4 size have their busses connected together. This
system will be of size[c ]
a) 16×4 b) 256×1 c)
16×16 d) 32×8
5. The parameters of a threshold element are [ a]
a) weights assigned
to input variable s and T b) output variables
c) weights assigned
to input variables d) value of T
6. The table containing
present state of output, next state of the output and the inputs is called[a ]
( a)
Excitationtable ( b ) State table ( c ) Transition table e ( d ) Truth table
7. A finite state machine [a]
(a) same as clocked
sequential circuits
(b) Neither Electrical
motors nor clocked sequential circuits
(c) consists of
electrical motors
(d) Electrical
motors and clocked sequential circuits
8. The address bus with a ROM of size 1024*8 bits is [ b]
a)8 bits b) 10 bits
c) 12 bits d) 16 bits
9. Which of the following flip flop is used as a latch – [b ]
a) JK flip flop b) D flip flop c)Master
Slave flip d) T flip flop
10. Master slave configuration is used in flip flop to [c ]
a) Increase its
clocking b) reduce power dissipation
c) Eliminate race
around condition d) improve its reliability
11.The
ROM programmed during manufacturing process itself is called [ a]
a)MROM (b) PROM (c) EPROM (d) EEPROM
12. A memory in which the contents get erased when power failure occurs
is [ d]
a)EAROM (b) PROM (c) ROM (d) RAM
13. A single literal term in SOP expression
[ b]
a)Requires an inverter for PLA
implementation
b)Requires an AND gate for PLA
implementation
c)Doesn’t requires an AND gate for PLA
implementation
d) Doesn’t requires an inverter for PLA
implementation
14. When an inverter is placed between the
inputs of an S – R flip – flop, the resulting flip – flop is a [ d]
a)J - K flip - flop (b) Master – slave flip
- flop c)T flip - flop (d) D flip - flop
15. Flip – flops can be used to make [c ]
a)Latches (b) Bounce – elimination switches
c) Registers (d) All of the above
16. The output of a clocked sequential
circuit is independent of the input. The circuit can be represented by [b ]
a)Mealy model (b) Moore model
c)Either Mealy or Moore model (d) Neither
Mealy or Moore model
17. For designing a finite state machine k
– maps can be used for minimizing the
[ d]
a)Excitation expressions of flip - flops
(b) Number of flip – flops
c)Output logic expressions (d) Excitation
and output logic expressions
18. While constructing a state diagram of
sequential circuit from the set of given statements [b ]
a)A minimum number of states must only be
used b)Redundant states may be used
c) Redundant states must be avoided d)None
of the above
19. An ASM chart consists of [ d]
a)Only state boxes (b) only decision boxes c)Only
decision and conditional output boxes (d) All the above.
20. Moore type outputs are [a ]
a)Independent of the inputs b)Dependent
only on the inputs
c)Dependent on present state and inputs
d)Any one of the above
21.
An n-stage ripple counter can count up to [b ]
(a) 2n (b) 2n-1 (c) n (d) 2n-1
22.
A mod-13 counter must have [ c]
(a) 13 flip flops (b) 3 flip flops (c) 4 flip flops (d)
synchronous clocking
23.
In programmable logic array [ c]
(a) AND –array is fixed &OR- array is programmable
(b) AND-array is programmable & OR-array is fixed
(c) both AND &OR array are programmable
(d) both AND &OR array are fixed
24.
Total no.of programmable fuses in ‘n’ input ‘m’ output PROM is [ c]
(a) n (b) nXm (c) 2nXm (d) 2mXn
25.
A decision box in an ASM chart [ c]
(a) does not have exit paths (b) have only one exit path
(c) has two exit paths (d) has one entry and has one exit
path
26.
The functional difference between an SR flip-flop and J-K flip-flop is that [ c]
(a) J-K flip-flop is faster (b) J-K flip-flop has
feedback
(c) J-K flip-flop accepts both inputs 1 (d) J-K flip-flop
does not require clock
27.
An Asynchronous counter differs from synchronous counter in [b ]
(a) Mod number (b) Method of clocking
(c) the type of flip-flops used (d) the numberof states
in a sequence
28.
To serially shift a byte of data in to shift register there must be [c ]
(a)1 clock pulse (b)one load pulse (c)eight clock pulses
d)one clock pulse in each 1 in the data
29.
Programming a PLD device means [b ]
(a) writing software program (b) blowing electronic fuses
(c) writing assembly language program (d) writing C
program
30.
When power supply of ROM is switched off, its contents [ c]
(a)
becomes zero (b) becomes all ones (c) remains same (d) are unpredictable
Section
-2:Fill in the blanks
1.A PLA consists of AND, OR and invert / non invert matrix
2. A ROM has 32K×8 organization. Its capacity in bits is 256
Kbits
3. The number of outputs of a threshold element is 1
4. A shift register using flip flop is called Static
shift register
5. The minimum number of flip flops required for a mod-12 ripple
counter is 4
6. A Johnson counter is also called as inverse feedback amplifier
7. If the outputs of two states are different after P-state
transitions they are said to be
P- Distinguishable
8. Unspecified outputs provide
additional flexibility on state reduction.
9. The Programmable Array Logic consists of Programmable
AND, fixed OR gates
10. The Moore type of output are represented inside the State
box
in an ASM chart
11.In a positive unite function all the variables are only in Un
complemented form.
12. Non threshold functions cannot be
realized using a single threshold gate.
13. Master – slave configuration is used in J-K flip – flops to
eliminate Race
around condition
14. A Basic
ring
counter requires no decoding circuitry.
15. The process of assigning the states of a physical device to the
states of a sequential machine is
known as State
assignment
16. The merger table method of state reduction is also called pull unger method or implication chart method.
17. A table which consists of the states of a minimal state machine is
called a minimal cover
table
18. The data processing path is commonly referred to as the data paths.
19. Moore type of outputs
are referred to as unconditional outputs.
20. A path through an ASM block from entry to exit is referred to as a
path
21. The sequential circuit is a combination of combinational
circuit and memory elements.
22. The characteristic equation of J-K flip flop is JQI+KIQ
23. If the binary word 1101 is entered serially into the 4-bit serial
in parallel out shift register (initially clear), the Q outputs after two clock
pulses are 0100
24. A combinational PLD with programmable AND array and programmable
OR array is called as
PLA
25. Next state variables in asynchronous sequential circuits are
called excitation
variables.
26. A counter that triggers all the flip-flops together is called synchronous counter.
27. In synchronous circuit output depends only on the present state of
flip-flop is called
Moore machine
28. The full form of PROM is programmable read only memory.
29. State diagram is a pictorial representation of
behavior of a sequential circuit.
30. A Jhonson counter uses D flip flops.
Prepared by
Sowmya & sreelatha
